1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a multi-chip IC package structure, which can be used to pack more than one IC chip therein and whose characterized structure allows a short bonding wire length so as to retain IC performance and save manufacture cost.
2. Description of Related Art
A multi-chip IC package is a type of IC package that is designed to enclose more than one IC chip therein, which can offer a manifold level of functionality than a single-chip IC package. Conventionally, there are many ways to pack more than one IC chip in a single package.
FIGS. 1A-1C are schematic sectional diagrams used to depict three different types of multi-chip IC package structures. FIG. 1A shows a stacked type that packs two IC chips 11a, 12a, in a stacked manner; FIG. 1B shows a juxtaposed type that packs two IC chips 21a, 22a by arranging them side by side on the same lead frame plane; and FIG. 1C shows a back-to-back type that arranges two IC chips 31a, 32a in a back-to-back manner.
One drawback to the forgoing types of multi-chip IC package structures, however, is that they are only suitable for use to pack IC chips of peripheral-pad type, but unsuitable for use to pack IC chips of central-pad type (in this specification, the term "central-pad IC chip"refers to an IC chip whose bonding pads are arranged in the center thereof, whereas the term "peripheral-pad IC chip" refers to an IC chip whose bonding pads are arranged near the peripheral edge thereof. This is because that if the multi-chip IC package structures of FIGS. 1A-1C are used to pack IC chips of central-pad type, it would require an increase in the bonding wire length, thus undesirably degrading the IC performance and increasing the manufacture cost. This drawback is illustratively depicted in FIGS. 2A-2C.
As shown in FIG. 2A, if the package structure of FIG. 1A is used to pack a peripheral-pad IC chip 11b and a central-pad IC chip 12b, then it requires the use of a set of bonding wires 13b of a greater length than the bonding wires 13a for the peripheral-pad IC chip 12a shown in FIG. 1A. As a consequence, it would degrade the IC performance and increase the overall manufacture cost.
As shown in FIG. 2B, if the package structure of FIG. 1B is used to pack two central-pad IC chips 21b, 22b, it requires the use of two sets of bonding wires 23b, 24b of a greater length than the bonding wires 23a, 24a for the peripheral-pad IC chip 21a, 22a shown in FIG. 1B. As a consequence, it would degrade the IC performance and increase the overall manufacture cost.
As further shown in FIG. 2C, if the package structure of FIG. 1C is used to pack two central-pad IC chips 31b, 32b, it requires the use of two sets of bonding wires 33b, 34b of a greater length than the bonding wires 33a, 34a for the peripheral-pad IC chips 31a, 32a shown in FIG. 1C. As a consequence, it would degrade the IC performance and increase the overall manufacture cost